The present invention relates to a voltage adder circuit that subjects a plurality of input voltages to weighted addition and a D/A converter circuit provided with the voltage adder circuit.
In some D/A converter circuits, input data that are an object of conversion are divided into high-order bits and low-order bits, and the high-order bits and the low-order bits are respectively subjected to D/A conversion. Respective results of D/A conversions are further subjected to weighted addition, whereby a final result of D/A conversion is produced. A D/A converter circuit of this type is described in; for instance, JP-A-2001-156640. The D/A converter circuit has two D/A converters and a voltage adder circuit. The two D/A converters perform D/A conversion of high-order four bits, among eight bits of input data, and a result of bit inversion of low-order four bits (i.e., one's complement of the low-order four bits). A voltage adder circuit subjects a voltage Va and a voltage Vb output from the two D/A converters to weighted addition. As shown in FIG. 3A, the D/A converter circuit described in JP-A-2001-156640 us es, as a voltage adder circuit that performs weighted addition of the voltage Va and the voltage Vb, a voltage adder circuit including two operational amplifiers OP1 and OP2 and two resistors ra and rb. In the voltage adder circuit, the resistors ra and rb are interposed between an output terminal OUT of the operational amplifier OP1 and an output terminal OUT of the operational amplifier OP2. The output terminal OUT of the operational amplifier OP1 is connected to a negative input terminal IN− of the same by way of the resistor ra, and the output terminal OUT of the operational amplifier OP2 is connected to a negative input terminal IN− of the same by bypassing the resistor. In such a configuration, a resistance ratio of the resistor ra to the resistor rb is taken as 1 to (2n−1), the voltage Va is input to a positive input terminal IN+ of the operational amplifier OP1, and the voltage Vb is input to a positive input terminal IN+ of the operational amplifier OP2. A voltage Vo equal to a result of weighted addition operation expressed by the following equation is output from the output terminal OUT of the operational amplifier OP1. The voltage Vo ideally comes to a voltage that linearly changes in response to the original 8-bit input data.Vo=(2n/(2n−1))Va−(1/(2n−1))Vb  (1)
However, in the voltage adder circuit having such a configuration, when a difference occurs between a voltage of the output terminal OUT of the operational amplifier OP1 and a voltage of the output terminal OUT of the operational amplifier OP2, an electric current flows between the output terminals OUT. As a result, an input offset voltage occurs between the positive input terminal IN+ and the negative input terminal IN− of the operational amplifier OP1, as well as occurring between the positive input terminal IN+ and the negative input terminal IN− of the operational amplifier OP2. In particular, the input voltage Va of the operational amplifier OP1 is multiplied by a large weighting coefficient (2n/(2n−1)) as expressed by Equation (1). The input offset occurred in the operational amplifier OP1 adversely affects a voltage Vo obtained from the output terminal OUT of the operational amplifier OP1, which in turn induces an error between an actually acquired voltage value Vo and an ideal voltage value Vo represented by Equation (1). An explanation is hereunder given to why the input offset occurs in the operational amplifier OP1.
FIG. 3B shows an example configuration of the operational amplifier OP1 and that of the operational amplifier OP2 used in the voltage adder circuit shown in FIG. 3A. In FIG. 3B, a gate of an N channel field effect transistor (hereinafter called simply as a “transistor”) N1 acts as the positive input terminal IN+ of the operational amplifier OP1 (OP2). A gate of an N channel transistor N2 serves as a negative input terminal IN− of the operational amplifier OP1 (OP2). Sources of the respective N channel transistors N1 and N2 are connected together, thereby forming a differential pair that amplifies a potential difference between the positive input terminal IN+ and the negative input terminal IN−. A drain of an N channel transistor N3 is connected to a common node between the sources of the N channel transistors N1 and N2, and a source of the N channel transistor N3 is connected to a ground. A reference level voltage Vref having a given reference level is applied to a gate of the N channel transistor N3 and acts as a constant current source that supplies a constant current having a given current value Iref. A drain of the P channel transistor P1 is connected to a drain of the N channel transistor N1, and a drain of the P channel transistor P2 is connected to a drain of the N channel transistor N2. Sources of the P channel transistors P1 and P2 are connected to a power source VDD, and respective gates of the P channel transistors P1 and P2 are connected to a drain of the N channel transistor N2, thereby acting as loads for the respective N channel transistors N1 and N2.
A source of the P channel transistor P3 is connected to the power source VDD, and a gate of the P channel transistor P3 is connected to a node between a drain of the N channel transistor N1 and a drain of the P channel transistor P1. A source of an N channel transistor N4 is connected to the ground, and a drain of the N channel transistor N4 is connected to a drain of a P channel transistor P3. The reference level voltage Vref is applied to a gate of the N channel transistor N4. The N channel transistor N4 acts as a constant current source that lets the given current Iref flow. A node between a drain of the P channel transistor P3 and a drain of the N channel transistor N4 acts as the output terminal OUT of the operational amplifier OP1 (OP2).
In the configuration shown in FIG. 3A, when one of a voltage of the output terminal OUT of the operational amplifier OP1 and a voltage of the output terminal OUT of the operational amplifier OP2 becomes higher than the other, an electric current flows from the output terminal OUT having a higher voltage toward the output terminal OUT having a lower voltage.
For instance, an electric current ΔI having a certain magnitude is assumed to flow from the operational amplifier OP1 to the operational amplifier OP2. In this case, in order to output the current ΔI from the output terminal OUT of the operational amplifier OP1 shown in FIG. 3B, a drain current flowing into the P channel transistor P3 must become higher than the current value Iref of the N channel transistor N4, which acts as a constant current source, by an amount of ΔI. To this end, provided that mutual conductance of the P channel transistor P3 is taken as gm, a gate voltage Vg of the P channel transistor P3 must be made lower by ΔI/gm when compared with the case where the current ΔI is not output from the output terminal OUT. In order to make the gate voltage Vg of the P channel transistor P3 lower by ΔI/gm, a drain potential of the N channel transistor N1 must be made lower by ΔI/gm as compared with a case where the electric current ΔI is not output from the output terminal OUT, and a drain potential of the N channel transistor N2 must be increased correspondingly. For these reasons, in a state where a negative feedback is sent from the output terminal OUT to the negative input terminal IN− by way of the resistor ra, an input voltage (a feedback voltage) of the negative input terminal IN− of the operational amplifier OP1 does not accurately match an input voltage of the positive input terminal IN+ and turns into a voltage that is lower than an input voltage of the positive input terminal IN+ by an offset voltage equal to the ΔI/gm. Conversely, when the electric current ΔI having a certain magnitude flows from the operational amplifier OP2 to the operational amplifier OP1, an input voltage (the feedback voltage) of the negative input terminal IN− of the operational amplifier OP1 turns into a voltage that has become higher than the input voltage of the positive input terminal IN+ by an offset voltage equal to the current ΔI.
As described above, the voltage Vo acquired from the output terminal OUT of the operational amplifier OP1 comes to a voltage including a difference from the voltage Vo that is expressed by Equation (1) and that exhibits ideal linearity. The problem is not limited to the voltage adder circuit used in the D/A converter circuit, such as that described in JP-A-2001-156640, but also occurs even in a voltage adder circuit used in a circuit other than the D/A converter circuit.